SGTL5000XNAA3 Datasheet, PDF (69/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
7.0.0.19. CHIP_CLK_TOP_CTRL
0x0034
Miscellaneous controls for the clock block.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
FIELD
RW RESET
DEFINITION
15:12 RESERVED RO 0x0
Reserved
11 ENABLE_INT_OS RW 0x0
C
Setting this bit enables an internal oscillator to be used for the
zero cross detectors, the short detect recovery, and the
charge pump. This will allow the I2S clock to be shut off while
still operating an analog signal path. This bit can be kept on
when the I2S clock is enabled, but the I2S clock is more
accurate so it is preferred to clear this bit when I2S is present.
10:4
RSVD
RW 0x0 Reserved
3 INPUT_FREQ_DI RW 0x0
V2
SYS_MCLK divider before PLL input
0x0 = pass through
0x1 = SYS_MCLK is divided by 2 before entering PLL
This must be set when the input clock is above 17Mhz. This
has no effect when the PLL is powered down.
2:0
RSVD
RW 0x0 Reserved
7.0.0.20. CHIP_ANA_STATUS
Status bits for analog blocks.
0x0036
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15:10
9
8
7:5
FIELD
RSVD
LRSHORT_STS
CSHORT_STS
RSVD
RW RESET
DEFINITION
RO 0x0 Reserved
RO 0x0
This bit is high whenever a short is detected on the left or right
channel headphone drivers.
0x0 = Normal
0x1 = Short detected
RO 0x0
This bit is high whenever a short is detected on the capless
headphone common/center channel driver.
0x0 = Normal
0x1 = Short detected
RO 0x0 Reserved
SGTL5000 EA2 DS-0-3
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