SGTL5000XNAA3 Datasheet, PDF (29/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
5.4.
Clocking
Clocking for the SGTL5000 is provided by a system master clock input
(SYS_MCLK). SYS_MCLK should be synchronous to the sampling rate (Fs) of the
I2S port. Alternatively any clock between 8Mhz and 27Mhz can be provided on
SYS_MCLK and the SGTL5000 can use an internal PLL to derive all internal and
I2S clocks. This allows the system to use an available clock such as 12MHz (com-
mon USB clock) for SYS_MCLK to reduce overall system costs.
5.4.1.
Synchronous SYS_MCLK input
The SGTL5000 supports various combinations of SYS_MCLK frequency and sam-
pling frequency as shown in Table 12. Using a synchronous SYS_MCLK allows for
lower power as the internal PLL is not used.
Table 12. Synchronous MCLK Rates
Clock
System Master Clock (SYS_MCLK)
Sampling Frequency (Fs)
Supported rates
256, 384, 512
8, 11.025, 16, 22.5, 32, 44.1, 48,
96(note 1)
Units
Fs
kHz
note 1. For a sampling frequency of 96kHz, only 256Fs SYS_MCLK is supported
5.4.2.
Using the PLL - Asynchronous SYS_MCLK input
An integrated PLL is provided in the SGTL5000 that allows any clock from 8MHz to
27MHz to be connected to SYS_MCLK. This can help save system costs as a clock
available elsewhere in the system can be used to derive all audio clocks using the
internal PLL. In this case the clock input to SYS_MCLK can be asynchronous with
the sampling frequency needed in the system. For example a 12MHz clock from the
system processor could be used as the clock input to the SGTL5000.
Three register fields need to be configured to properly use the PLL. They are
CHIP_PLL_CTRL->INT_DIVISOR, CHIP_PLL_CTRL->FRAC_DIVISOR and
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2. Figure 11 shows a flowchart that
shows how to determine the values to program in the register fields.
SGTL5000 EA2 DS-0-3
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