SGTL5000XNAA3 Datasheet, PDF (43/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
Table 14. Write Auto increment
S Device W A start A start A DATA A DATA A DATA A DATA A P
Address (0)
ADDR
ADDR
[n]
[n]
[n+1]
[n+1]
byte 1
byte 0
byte 1
byte 0
byte 1
byte 0
Table 15. Read Single Location
S Device W A ADDR A ADDR A Sr Device R A DATA A DATA N P
Address (0)
byte 1
byte 0
Address (1)
byte 1
byte 0
Table 16. Read Auto increment
S Device W A start A start A Sr Device R A DATA A DATA A DATA A DATA N P
Address (0) ADDR ADDR
Address (1)
[n]
[n]
[n+1]
[n+1]
byte 1 byte 0
byte 1 byte 0 byte 1 byte 0
Table 17. Read Continuing Auto increment
S
Device
RA
DATA
A
DATA
A
DATA
A
DATA
NP
Address
[n+2]
[n+2]
[n+3]
[n+3]
byte 1
byte 0
byte 1
byte 0
5.10.2.
SPI
Serial Peripheral Interface (SPI) is a communications protocol supported by the
SGTL5000. The SGTL5000 is always a slave. The CTRL_AD0_CS is used as the
slave select (SS) when the master wants to select the SGTL5000 for communica-
tion. CTRL_CLK is connected to master’s SCLK and CTRL_DATA is connected to
master’s MOSI line. The part only supports allows SPI write operations and does
not support read operations.
Figure 20 below shows the functional timing diagram of the SPI communication pro-
tocol as supported by SGTL5000 chip. Note that on the rising edge of the SS, the
chip latches to previous 32 bits of data. It interprets the latest 16-bits as register
value and 16-bits preceding it as register address.
On rising edge of SS, latch
the last 32 bits of data
SS
31
SCK
MOSI
Addr Addr
15 14
16-bits Register Address
23
15
Addr
Addr Addr
8
76
Addr
Val Val
0
15 14
16-bits Register Value
7
0
Val
Val Val
Val
8
76
0
Figure 20. Functional Timing Diagram of SPI Protocol
SGTL5000 EA2 DS-0-3
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