SGTL5000XNAA3 Datasheet, PDF (56/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
BITS
8
7
6
5:4
3:2
1
0
FIELD
SCLKFREQ
MS
SCLK_INV
DLEN
I2S_MODE
LRALIGN
LRPOL
RW RESET
DEFINITION
RW 0x0
Sets frequency of I2S_SCLK when in master mode (MS=1).
When in slave mode (MS=0), this field must be set
appropriately to match SCLK input rate.
0x0 = 64Fs
0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
RW 0x0
Configures master or slave of I2S_LRCLK and I2S_SCLK.
0x0 = Slave: I2S_LRCLK and I2S_SCLK are inputs
0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
NOTE: If the PLL is used (CHIP_CLK_CTRL-
>MCLK_FREQ==0x3), the SGTL5000 must be a master of the
I2S port (MS==1)
RW 0x0
Sets the edge that data (input and output) is clocked in on for
I2S_SCLK
0x0 = data is valid on rising edge of I2S_SCLK
0x1 = data is valid on falling edge of I2S_SCLK
RW 0x1
I2S data length
0x0 = 32 bits (only valid when SCLKFREQ=0), not valid for
Right Justified Mode
0x1 = 24 bits (only valid when SCLKFREQ=0)
0x2 = 20 bits
0x3 = 16 bits
RW 0x0
Sets the mode for the I2S port
0x0 = I2S mode or Left Justified (Use LRALIGN to select)
0x1 = Right Justified Mode
0x2 = PCM Format A/B
0x3 = RESERVED
RW 0x0
I2S_LRCLK Alignment to data word. Not used for Right
Justified mode
0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
transition (I2S format, PCM format A)
0x1 = Data word starts after I2S_LRCLK transition (left
justified format, PCM format B)
RW 0x0
I2S_LRCLK Polarity when data is presented.
0x0 = I2S_LRCLK = 0 - Left, 1 - Right
1x0 = I2S_LRCLK = 0 - Right, 1 - Left
The left subframe should be presented first regardless of the
setting of LRPOL.
7.0.0.5. CHIP_SSS_CTRL
0x000A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15
FIELD
RSVD
RW RESET
RW 0x0 Reserved
56
DEFINITION
SGTL5000 EA2 DS-0-3