SGTL5000XNAA3 Datasheet, PDF (42/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
• Send two bytes for the 16 bits of data to be written to the register (most signifi-
cant byte first)
• Stop condition
An I2C read transaction is defined as follows:
• Start condition
• Device address with the R/W bit cleared to indicate write
• Send two bytes for the 16 bit register address (most significant byte first)
• Stop Condition followed by start condition (or a single restart condition)
• Device address with the R/W bit set to indicate read
• Read two bytes from the addressed register (most significant byte first)
• Stop condition
Figure 19 shows the functional I2C timing diagram.
I2C Address
Start Condition
R/W ACK A15
A8 ACK A7
A0 ACK D15
Figure 19. Functional I2C Diagram
D8 ACK D7
D0 ACK
Stop Condition
The protocol has an auto increment feature. Instead of sending the stop condition
after two bytes of data, the master may continue to send data byte pairs for writing,
or it may send extra clocks for reading data byte pairs. In either case, the access
address is incremented after every two bytes of data. A start or stop condition from
the I2C master interrupts the current command. For reads, unless a new address is
written, a new start condition with R/W=0 reads from the current address and contin-
ues to auto increment.
The following diagrams describe the different access formats. The gray fields are
from the I2C master, and the white fields are the SGTL5000 responses. Data[n] cor-
responds to the data read from the address sent, data[n+1] is the data from the next
register, and so on.
S = Start Condition
Sr = Restart Condition
A = Ack
N = Nack
P = Stop Condition
TA2 silicon will allow for up to a 3.6V I2C signal level, regardless of the VDDIO level.
S
Device
Address
Table 13. Write Single Location
W A ADDR A ADDR A DATA A DATA A P
(0)
byte 1
byte 0
byte 1
byte 0
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SGTL5000 EA2 DS-0-3