SGTL5000XNAA3 Datasheet, PDF (28/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
Note that if VDDA and VDDIO are derived from the same voltage, a single decou-
pling capacitor can be used to minimize cost. This capacitor should be placed clos-
est to VDDA.
• VDDD: This is a digital power supply that is used for internal digital circuitry. For
a low cost design, this supply can be derived from an internal regulator and no
external components are required. If no external supply is applied to VDDD, the
internal regulator will automatically be used. For lowest power, this supply can
be driven at the lowest specified voltage given in section 1.2. If an external sup-
ply is used for VDDD, a decoupling capacitor is recommended. VDDD supply
ranges are shown in section 1.2 for when externally driven. If the system drives
VDDD externally, an efficient switching supply should be used or or no system
power savings will be realized.
5.2.2.
Internal Power Supplies
The SGTL5000 has two exposed internal power supplies, VAG and chargepump.
• VAG is the internal voltage reference for the ADC and DAC. After startup the
voltage of VAG should be set to VDDA/2 by writing CHIP_REF_CTRL-
>VAG_VAL. Refer to programming section 6.2.1.1. The VAG pin should have an
external filter capacitor as shown in the typical connection diagram.
• Chargepump: This power supply is used for internal analog switches. If VDDA
or VDDIO is greater than 2.7V, this supply is automatically driven from the high-
est of VDDIO and VDDA. If both VDDIO and VDDA are less than 3.1V, then the
user should turn on the charge pump function to create the chargepump rail
from VDDIO by writing CHIP_ANA_POWER->VDDC_CHRGPMP_POWERUP
register. Refer to programming section 6.2.1.1.
• LINE_OUT_VAG is the line output voltage reference. It should be set to
VDDIO/2 by writing CHIP_LINE_OUT_CTRL->LO_VAGCNTRL.
5.2.3.
Power Schemes
The SGTL supports a flexible architecture and allows the system designer to mini-
mize power or maximize BOM savings.
• For maximum cost savings, all supplies can be run at the same voltage.
• Alternatively for minimum power, the analog and digital supplies can be run at
minimum voltage while driving the digital I/O voltage at the voltage needed by
the system.
• To save power, independent supplies are provided for line outputs and head-
phone outputs. This allows for 1VRMS line outputs while using minimal head-
phone power.
• For best power, VDDA should be run at the lowest possible voltage required for
the maximum headphone output level. For highest performance, VDDA should
be run at 3.3V. For most applications a lower voltage can be used for the best
performance/power combination.
5.3. Reset
The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLKs after all
power rails have been brought up. After this time communication can start. See sec-
tion 1.3 for timing specification.
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SGTL5000 EA2 DS-0-3