SGTL5000XNAA3 Datasheet, PDF (55/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
7.0.0.3. CHIP_CLK_CTRL
0x0004
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15:6
5:4
3:2
1:0
FIELD
RSVD
RATE_MODE
SYS_FS
MCLK_FREQ
RW RESET
DEFINITION
RO 0x0 Reserved
RW 0x0
Sets the sample rate mode. MCLK_FREQ is still specified
relative to the rate in SYS_FS
0x0 = SYS_FS specifies the rate
0x1 = Rate is 1/2 of the SYS_FS rate
0x2 = Rate is 1/4 of the SYS_FS rate
0x3 = Rate is 1/6 of the SYS_FS rate
RW 0x2
Sets the internal system sample rate
0x0 = 32 kHz
0x1 = 44.1 kHz
0x2 = 48 kHz
0x3 = 96 kHz
RW 0x0
Identifies incoming SYS_MCLK frequency and if the PLL
should be used
0x0 = 256*Fs
0x1 = 384*Fs
0x2 = 512*Fs
0x3 = Use PLL
The 0x3 (Use PLL) setting must be used if the SYS_MCLK is
not a standard multiple of Fs (256, 384 or 512). This setting
can also be used if SYS_MCLK is a standard multiple of Fs.
Before this field is set to 0x3 (Use PLL), the PLL must be
powered up by setting CHIP_ANA_POWER-
>PLL_POWERUP and CHIP_ANA_POWER-
>VCOAMP_POWERUP. Also, the PLL dividers must be
calculated based on the external MCLK rate and
CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL
register description details on how to calculate the divisors).
7.0.0.4. CHIP_I2S_CTRL
0x0006
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15:9
FIELD
RSVD
RW RESET
RO 0x0 Reserved
DEFINITION
SGTL5000 EA2 DS-0-3
55