SGTL5000XNAA3 Datasheet, PDF (63/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
BITS
FIELD
RW RESET
DEFINITION
5 VDDC_ASSN_OV RW 0x0
RD
Chargepump Source Assignment Override
0x0 = Chargepump source is automatically assigned based
on higher of VDDA and VDDIO
0x1 = the source of chargepump is manually assigned by
VDDC_MAN_ASSN
If VDDIO and VDDA are both the same and greater than
3.1V, VDDC_ASSN_OVRD and VDDC_MAN_ASSN should
be used to manually assign VDDIO as the source for
chargepump.
4
RSVD
RW 0x0 Reserved
3:0 D_PROGRAMMI RW 0x0
NG
Sets the VDDD lin. regulator output voltage in 50mV steps.
Must clear pwd_linreg_d bit to enable this lin reg.
0x0=1.60
0xF=0.85
7.0.0.13. CHIP_REF_CTRL
0x0028
This register controls the bandgap reference bias voltage and currents.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15:9
8:4
3:1
0
FIELD
RSVD
VAG_VAL
BIAS_CTRL
SMALL_POP
RW RESET
DEFINITION
RO 0x0 Reserved
RW 0x0
Analog Ground Voltage Control
These bits control the analog ground voltage in 25mV steps.
This should usually be set to VDDA/2 or lower for best
performance (maximum output swing at minimum THD). This
VAG reference is also used for the DAC and ADC voltage
reference. So changing this voltage scales the output swing
of the DAC and the output signal of the ADC.
0x00 = 0.800V
0x1F = 1.575V
RW 0x0
Bias control
These bits adjust the bias currents for all of the analog blocks.
By lowering the bias current a lower quiescent power is
achieved. It should be noted that this mode can affect
perfomance by 3-4dB.
0x0 = Nominal
0x1-0x3=+12.5%
0x4=-12.5%
0x5=-25%
0x6=-37.5%
0x7=-50%
RW 0x0
VAG Ramp Control
Setting this bit slows down the VAG ramp from ~200ms to
~400ms to reduce the startup pop, but increases the turn on/
off time.
0x0 = Normal VAG ramp
0x1 = Slowdown VAG ramp
SGTL5000 EA2 DS-0-3
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