SGTL5000XNAA3 Datasheet, PDF (30/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
Yes SYS_MCLK>17MHz? No
CHIP_CLK_TOP _CTRL->INPUT_FREQ_DIV2 = 1
PLL_INPUT_FREQ = SYS_MCLK/2
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0
PLL_INPUT_FREQ = SYS_MCLK
Sampling
Yes
Frequency =
No
44.1kHz?
PLL_OUTPUT_FREQ=180 .6336 MHz
PLL_OUTPUT_FREQ=196 .608 MHz
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (PLL_OUTPUT_FREQ/INPUT_FREQ
CHIP_PLL_CTRL->FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR) * 2048
Figure 11. PLL Programming Flowchart
For example, when a 12MHz digital signal is placed on MCLK, for a 48kHz frame
clock
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 // SYS_MCLK<17MHz
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR(196.608MHz/12MHz) = 16 (decimal)
CHIP_PLL_CTRL->FRAC_DIVISOR = ((196.608MHz/12MHz) - 16) * 2048 = 786
(decimal)
Refer to PLL programming note 6.2.2.
5.5. Audio Switch (Source Select Switch)
The audio switch is the central routing block that controls the signal flow from input
to output. Any single input can be routed to any single or multiple outputs.
Any signal can be routed to the Digital Audio Processor (DAP). The output of the
DAP (an input to the audio switch) can in turn be routed to any physical output. The
output of the DAP can not be routed into itself. Refer to section 5.9, Digital Audio
Processing, for DAP information and configuration.
It should be noted that the analog bypass from Line input to headphone output does
not go through the audio switch.
30
SGTL5000 EA2 DS-0-3