SGTL5000XNAA3 Datasheet, PDF (71/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
BITS
0
FIELD
TESTMODE
RW RESET
DEFINITION
RW 0x0 Enable the analog testmode paths
7.0.0.22. CHIP_ANA_TEST2
0x003A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
FIELD
RW RESET
DEFINITION
15
RSVD
RO 0x0 Reserved
14 LINEOUT_TO_VD RW 0x0
DA
Changes the lineout amplifier power supply from VDDIO to
VDDA. Typically lineout should be on the higher power
supply. This bit is useful when VDDA is ~3.3V and VDDIO is
~1.8V.
13
SPARE
RW 0x0 Spare registers to analog.
12 MONOMODE_DA RW 0x0
C
Copy the left channel DAC data to the right channel. This
allows both left and right to play from MONO dac data.
11 VCO_TUNE_AGA RW 0x0
IN
When toggled high then low forces the PLL VCO to retune the
number of inverters in the ring oscillator loop.
10 LO_PASS_MAST RW 0x0
ERVAG
Tie the main analog VAG to the lineout VAG. This can improve
SNR for the lineout when both are the same voltage.
9 INVERT_DAC_SA RW 0x0
MPLE_CLOCK
Change the clock edge used for the DAC output sampling.
8 INVERT_DAC_D RW 0x0
ATA_TIMING
Change the clock edge used for the digital to analog DAC data
crossing.
7 DAC_EXTEND_R RW 0x0
TZ
Extend the return-to-zero time for the DAC.
6 DAC_DOUBLE_I RW 0x0
Double the output current of the DAC amplifier when it is in
classA mode.
5 DAC_DIS_RTZ RW 0x0 Turn off the return-to-zero in the DAC. In mode cases this will
hurt the SNDR of the DAC.
4 DAC_CLASSA RW 0x0 Turn off the classAB mode in the DAC amplifier. This mode
should normally not be used. The output current will not be
high enough to support a full scale signal in this mode.
3 INVERT_ADC_SA RW 0x0
MPLE_CLOCK
Change the clock edge used for the ADC sampling.
2 INVERT_ADC_D RW 0x0
ATA_TIMING
Change the clock edge used for the analog to digital ADC data
crossing
1
ADC_LESSI RW 0x0 Drops ADC bias currents by 20%
SGTL5000 EA2 DS-0-3
71