MKL04Z32VFK4 Datasheet, PDF (648/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Memory map and register definition
GPIO memory map (continued)
Absolute
address
(hex)
Register name
400F_F044 Port Set Output Register (GPIOB_PSOR)
400F_F048 Port Clear Output Register (GPIOB_PCOR)
400F_F04C Port Toggle Output Register (GPIOB_PTOR)
400F_F050 Port Data Input Register (GPIOB_PDIR)
400F_F054 Port Data Direction Register (GPIOB_PDDR)
Width
(in bits)
Access
Reset value
Section/
page
W
32 (always 0000_0000h 37.2.2/649
reads 0)
W
32 (always 0000_0000h 37.2.3/649
reads 0)
W
32 (always 0000_0000h 37.2.4/650
reads 0)
32
R
0000_0000h 37.2.5/650
32
R/W 0000_0000h 37.2.6/651
37.2.1 Port Data Output Register (GPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output
pins.
NOTE
Do not modify pin configuration registers associated with pins
not available in your selected package. All un-bonded pins not
available in your package will default to DISABLE state for
lowest power consumption.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
PDO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDOR field descriptions
Field
31–0
PDO
Port Data Output
Description
Register bits for un-bonded pins return a undefined value when read.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
648
Freescale Semiconductor, Inc.