MKL04Z32VFK4 Datasheet, PDF (234/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Reset memory map and register descriptions
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x82
• LVD (without POR) — 0x02
• VLLS mode wakeup due to RESET pin assertion — 0x41
• VLLS mode wakeup due to other wakeup sources — 0x01
• Other reset — a bit is set if its corresponding reset source
caused the reset
Address: 4007_F000h base + 0h offset = 4007_F000h
Bit
Read
Write
Reset
7
POR
1
6
5
PIN
WDOG
0
0
4
3
0
0
0
2
LOC
0
1
LVD
0
WAKEUP
1
0
RCM_SRS0 field descriptions
Field
7
POR
Power-On Reset
Description
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset
occurred while the internal supply was below the LVD threshold.
0 Reset not caused by POR
1 Reset caused by POR
6
External Reset Pin
PIN
Indicates a reset has been caused by an active-low level on the external RESET pin.
5
WDOG
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
Watchdog
Indicates a reset has been caused by the watchdog timer Computer Operating Properly (COP) timing out.
This reset source can be blocked by disabling the COP watchdog: write 00 to the SIM's COPC[COPT]
field.
4–3
Reserved
2
LOC
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
This field is reserved.
This read-only field is reserved and always has the value 0.
Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled
for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the
clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Table continues on the next page...
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
234
Freescale Semiconductor, Inc.