MKL04Z32VFK4 Datasheet, PDF (285/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Chapter 19 Micro Trace Buffer (MTB)
19.31.15 Component ID Register (MTB_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
COMPID
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for the reset values.x = Undefined at reset.
Field
31–0
COMPID
MTB_COMPIDn field descriptions
Component ID
Description
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
19.3.2 MTB_DWT Memory Map
The MTB_DWT programming model supports a very simplified subset of the v7M debug
architecture and follows the standard ARM DWT definition.
MTBDWT memory map
Absolute
address
(hex)
Register name
F000_1000 MTB DWT Control Register (MTBDWT_CTRL)
F000_1020 MTB_DWT Comparator Register (MTBDWT_COMP0)
F000_1024 MTB_DWT Comparator Mask Register (MTBDWT_MASK0)
F000_1028
MTB_DWT Comparator Function Register 0
(MTBDWT_FCT0)
F000_1030 MTB_DWT Comparator Register (MTBDWT_COMP1)
F000_1034 MTB_DWT Comparator Mask Register (MTBDWT_MASK1)
F000_1038
MTB_DWT Comparator Function Register 1
(MTBDWT_FCT1)
F000_1200
MTB_DWT Trace Buffer Control Register
(MTBDWT_TBCTRL)
F000_1FC8 Device Configuration Register (MTBDWT_DEVICECFG)
Width
(in bits)
Access
32
R
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R
Reset value
2F00_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
2000_0000h
0000_0000h
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KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
285