MKL04Z32VFK4 Datasheet, PDF (513/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

counter overflow
timer module counter =
MOD
Chapter 30 Timer/PWM Module (TPM)
timer module counter = 0
channel (n) match
(timer module counting
is down)
channel (n) match
counter overflow
(timer module counting _{timer module counter =}
is up)
MOD
channel (n) output
pulse width
(2 x CnV)
period
(2 x MOD)
Figure 30-69. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the TPM counter reaches the value in the CnV register,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by TPM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (TPM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up (see the following figure).
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
counter
overflow
channel (n) match in
down counting
CNT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8
channel (n) output
CHnF bit
previous value
TOF bit
Figure 30-70. CPWM signal with ELSnB:ELSnA = 1:0
76
5 ...
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (TPM counter = CnV) when counting down, and it is forced high at the channel (n)
match when counting up (see the following figure).
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
counter
overflow
channel (n) match in
down counting
CNT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8
channel (n) output
CHnF bit
previous value
TOF bit
Figure 30-71. CPWM signal with ELSnB:ELSnA = X:1
76
5 ...
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
513