MKL04Z32VFK4 Datasheet, PDF (159/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Field
23–20
Reserved
19–16
IRQC
15–11
Reserved
10–8
MUX
7
Reserved
6
DSE
Chapter 11 Port control and interrupts (PORT)
PORTx_PCRn field descriptions (continued)
Description
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
This field is reserved.
This read-only field is reserved and always has the value 0.
Interrupt Configuration
This field is read only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:
0000
0001
0010
0011
1000
1001
1010
1011
1100
Others
Interrupt/DMA request disabled.
DMA request on rising edge.
DMA request on falling edge.
DMA request on either edge.
Interrupt when logic zero.
Interrupt on rising edge.
Interrupt on falling edge.
Interrupt on either edge.
Interrupt when logic one.
Reserved.
This field is reserved.
This read-only field is reserved and always has the value 0.
Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
This field is reserved.
This read-only field is reserved and always has the value 0.
Drive Strength Enable
This bit is read only for pins that do not support a configurable drive strength.
Drive strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
Table continues on the next page...
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
159