MKL04Z32VFK4 Datasheet, PDF (239/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify-
write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. This architectural capability is also known as "decorated storage" as it
defines a mechanism for providing additional semantics for load and store operations to
memory-mapped peripherals beyond just the reading and writing of data values to the
addressed memory locations. In the BME definition, the "decoration", that is, the
additional semantic information, is encoded into the peripheral address used to reference
the memory.
By combining the basic load and store instructions of the Cortex-M instruction set
architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the
resulting implementation provides a robust and efficient read-modify-write capability to
this class of ultra low-end microcontrollers. The resulting architectural capability defined
by this core platform function is targeted at the manipulation of n-bit fields in peripheral
registers and is consistent with I/O hardware addressing in the Embedded C standard. For
most BME commands, a single core read or write bus cycle is converted into an atomic
read-modify-write, that is, an indivisible "read followed by a write" bus sequence.
BME decorated references are only available on system bus transactions generated by the
processor core and targeted at the standard 512 KB peripheral address space based at
0x4000_0000¹. The decoration semantic is embedded into address bits[28:19], creating a
448 MB space at addresses 0x4400_0000 - 0x5FFF_FFFF; these bits are stripped out of
the actual address sent to the peripheral bus controller and used by the BME to define and
control its operation.
1. To be perfectly accurate, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family.
Attempted accesses to the memory space located between 0x4008_0000 - 0x400E_FFFF are error terminated due to an
illegal address.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
239