MKL04Z32VFK4 Datasheet, PDF (428/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Register definition
ADCx_CFG2 field descriptions (continued)
Field
Description
Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK
cycles added to the conversion time to allow higher speed conversion clocks.
1–0
ADLSTS
0 Normal conversion sequence selected.
1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
Long Sample Time Select
Selects between the extended sample times when long sample time is selected, that is, when
CFG1[ADLSMP]=1. This allows higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption when continuous conversions are enabled if high conversion rates are not required.
00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
01 12 extra ADCK cycles; 16 ADCK cycles total sample time.
10 6 extra ADCK cycles; 10 ADCK cycles total sample time.
11 2 extra ADCK cycles; 6 ADCK cycles total sample time.
28.3.4 ADC Data Result Register (ADCx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel
selected by the corresponding status and channel control register (SC1A:SC1n). For
every status and channel control register, there is a corresponding data result register.
Unused bits in R n are cleared in unsigned right-justified modes and carry the sign bit
(MSB) in sign-extended 2's complement modes.
The following table describes the behavior of the data result registers in the different
modes of operation.
Table 28-35. Data result register description
Conversion
mode
12-bit single-
ended
10-bit single-
ended
8-bit single-
ended
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Format
0 0 0 0 D D D D D D D D D D D D Unsigned right-
justified
0 0 0 0 0 0 D D D D D D D D D D Unsigned right-
justified
0 0 0 0 0 0 0 0 D D D D D D D D Unsigned right-
justified
NOTE
S: Sign bit or sign bit extension;
D: Data, which is 2's complement data if indicated
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
428
Freescale Semiconductor, Inc.