MKL04Z32VFK4 Datasheet, PDF (489/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

29.13.1 Voltage reference source select
Chapter 29 Comparator (CMP)
• V_in1 connects to the primary voltage source as supply reference of 64 tap resistor
ladder
• V_in2 connects to an alternate voltage source
29.14 DAC resets
This module has a single reset input, corresponding to the chip-wide peripheral reset.
29.15 DAC clocks
This module has a single clock input, the bus clock.
29.16 DAC interrupts
This module has no interrupts.
29.17 CMP Trigger Mode
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
1. In addition, the CMP must be enabled. If the DAC is to be used as a reference to the
CMP, it must also be enabled.
CMP Trigger mode depends on an external timer resource to periodically enable the
CMP and 6-bit DAC in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external
timer resource trigger is received.
See the chip configuration chapter for details about the external timer resource.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
489