MKL04Z32VFK4 Datasheet, PDF (519/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Chapter 31 Periodic Interrupt Timer (PIT-RTI)
31.3 Memory map/register description
This section provides a detailed description of all registers accessible in the PIT module.
NOTE
• Reserved registers will read as 0, writes will have no effect.
• See the chip configuration details for the number of PIT channels used in this MCU.
Address Offset
Channel + 0x00
Channel + 0x04
Channel + 0x08
Channel + 0x0C
Table 31-2. Timer Channel n
Use
Timer Load Value Register
Current Timer Value Register
Timer Control Register
Timer Flag Register
Access
R/W
R
R/W
R/W
PIT memory map
Absolute
address
(hex)
Register name
4003_7000 PIT Module Control Register (PIT_MCR)
4003_70E0 PIT Upper Lifetime Timer Register (PIT_LTMR64H)
4003_70E4 PIT Lower Lifetime Timer Register (PIT_LTMR64L)
4003_7100 Timer Load Value Register (PIT_LDVAL0)
4003_7104 Current Timer Value Register (PIT_CVAL0)
4003_7108 Timer Control Register (PIT_TCTRL0)
4003_710C Timer Flag Register (PIT_TFLG0)
4003_7110 Timer Load Value Register (PIT_LDVAL1)
4003_7114 Current Timer Value Register (PIT_CVAL1)
4003_7118 Timer Control Register (PIT_TCTRL1)
4003_711C Timer Flag Register (PIT_TFLG1)
Width
(in bits)
Access
Reset value
Section/
page
32
R/W 0000_0002h 31.3.1/519
32
R
0000_0000h 31.3.2/521
32
R
0000_0000h 31.3.3/521
32
R/W 0000_0000h 31.3.4/522
32
R
0000_0000h 31.3.5/522
32
R/W 0000_0000h 31.3.6/523
32
R/W 0000_0000h 31.3.7/524
32
R/W 0000_0000h 31.3.4/522
32
R
0000_0000h 31.3.5/522
32
R/W 0000_0000h 31.3.6/523
32
R/W 0000_0000h 31.3.7/524
31.3.1 PIT Module Control Register (PIT_MCR)
This register enables or disables the PIT timer clocks and controls the timers when the
PIT enters the Debug mode.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
519