MKL04Z32VFK4 Datasheet, PDF (526/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Initialization and application information
Timer enabled
Start value = p1
New start
Value p2 set
Trigger
event
p1
p1
p1
p2
p2
Figure 31-19. Dynamically setting a new load value
31.4.1.2 Debug mode
In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid
software development, allowing the developer to halt the processor, investigate the
current state of the system, for example, the timer values, and then continue the
operation.
31.4.2 Interrupts
All the timers support interrupt generation. See the MCU specification for related vector
addresses and priorities.
Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 when
a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to the
corresponding TFLGn[TIF].
31.4.3 Chained timers
When a timer has chain mode enabled, it will only count after the previous timer has
expired. So if timer n-1 has counted down to 0, counter n will decrement the value by
one. This allows to chain some of the timers together to form a longer timer. The first
timer (timer 0) cannot be chained to any other timer.
31.5 Initialization and application information
In the example configuration:
• The PIT clock has a frequency of 50 MHz.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
526
Freescale Semiconductor, Inc.