MKL04Z32VFK4 Datasheet, PDF (358/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Initialization / Application information
resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits
are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output
frequency is 83.89 MHz at high-range.
In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal
reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication
factor could potentially push the microcontroller system clock out of specification and
damage the part.
24.5.3 MCG mode switching
When switching between operational modes of the MCG, certain configuration bits must
be changed in order to properly move from one mode to another. Each time any of these
bits are changed (C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), the
corresponding bits in the MCG status register (IREFST, CLKST, IRCST, or OSCINIT)
must be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV])
is set properly for the mode being switched to. For instance, in FEE mode, if using a
4MHz crystal, C1[FRDIV] must be set to 3'b010 (divide-by-128) to devide the external
frequency down to the required frequency between 31.25 and 39.0625 kHz.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL
multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits.
Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1.
The table below shows MCGOUTCLK frequency calculations using C1[FRDIV]settings
for each clock mode.
Table 24-12. MCGOUTCLK Frequency Calculation Options
Clock Mode
FEI (FLL engaged internal)
FEE (FLL engaged external)
FBE (FLL bypassed external)
FBI (FLL bypassed internal)
BLPI (Bypassed low power internal)
BLPE (Bypassed low power external)
f_MCGOUTCLK1
(f_int * F)
(f_ext / FLL_R) *F
OSCCLK
MCGIRCLK
MCGIRCLK
OSCCLK
Note
Typical f_MCGOUTCLK = 21 MHz
immediately after reset.
f_ext / FLL_R must be in the range of
31.25 kHz to 39.0625 kHz
OSCCLK / FLL_R must be in the
range of 31.25 kHz to 39.0625 kHz
Selectable between slow and fast
IRC
Selectable between slow and fast
IRC
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and
C4[DMX32] bits.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
358
Freescale Semiconductor, Inc.