MKL04Z32VFK4 Datasheet, PDF (114/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Reset
6.2.2.4 Low leakage wakeup (LLWU)
The LLWU module provides the means for a number of external pins and a number of
internal peripherals to wake the MCU from low leakage power modes. The LLWU
module is functional only in low leakage power modes. In VLLSx modes, all enabled
inputs to the LLWU can generate a system reset.
After a system reset, the LLWU retains the flags indicating the input source of the last
wakeup until the user clears them.
NOTE
Some flags are cleared in the LLWU and some flags are
required to be cleared in the peripheral module. Refer to the
individual peripheral chapters for more information.
6.2.2.5 Multipurpose clock generator loss-of-clock (LOC)
The MCG module supports an external reference clock.
If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the
external reference falls below f_{loc_low} or f_{loc_high}, as controlled by the C2[RANGE] field
in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this
reset source.
NOTE
To prevent unexpected loss of clock reset events, all clock
monitors must be disabled before entering any low power
modes, including VLPR and VLPW.
6.2.2.6 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter stop mode or Compute Operation, but
not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to stop mode if an error condition occurs. The
error can be caused by a failure of an external clock input to a module.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
114
Freescale Semiconductor, Inc.