MKL04Z32VFK4 Datasheet, PDF (647/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

37.1.3.1
Chapter 37 General-Purpose Input/Output (GPIO)
Detailed signal description
Table 37-3. GPIO interface-detailed signal descriptions
Signal
I/O
PORTA31–PORTA0
I/O
PORTB31–PORTB0
Description
General-purpose input/output
State meaning
Asserted: The pin is logic 1.
Deasserted: The pin is logic 0.
Timing
Assertion: When output, this
signal occurs on the rising-
edge of the system clock. For
input, it may occur at any time
and input may be asserted
asynchronously to the system
clock.
Deassertion: When output,
this signal occurs on the
rising-edge of the system
clock. For input, it may occur
at any time and input may be
asserted asynchronously to
the system clock.
37.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error.
GPIO memory map
Absolute
address
(hex)
Register name
400F_F000 Port Data Output Register (GPIOA_PDOR)
400F_F004 Port Set Output Register (GPIOA_PSOR)
400F_F008 Port Clear Output Register (GPIOA_PCOR)
400F_F00C Port Toggle Output Register (GPIOA_PTOR)
400F_F010
400F_F014
400F_F040
Port Data Input Register (GPIOA_PDIR)
Port Data Direction Register (GPIOA_PDDR)
Port Data Output Register (GPIOB_PDOR)
Width
(in bits)
Access
Reset value
Section/
page
32
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W
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reads 0)
32
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Table continues on the next page...
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
647