MKL04Z32VFK4 Datasheet, PDF (566/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Memory Map and Register Descriptions
SPI0_S field descriptions (continued)
Field
6
SPMF
Description
0 No data available in the receive data buffer
1 _{Data available in the receive data buffer}
SPI match flag
SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the M register.
To clear the flag, read SPMF when it is set and then write a 1 to it.
5
SPTEF
0 Value in the receive data buffer does not match the value in the M register
1 Value in the receive data buffer matches the value in the M register
SPI transmit buffer empty flag
This bit is set when the transmit data buffer is empty. When the transmit DMA request is disabled
(TXDMAE is 0), SPTEF is cleared by reading the S register with SPTEF set and then writing a data value
to the transmit buffer at D. The S register must be read with SPTEF set to 1 before writing data to the D
register; otherwise, the D write is ignored. When the transmit DMA request is enabled (TXDMAE is 1),
SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed (TX
DMA Done is asserted). SPTEF is automatically set when all data from the transmit buffer transfers into
the transmit shift register. For an idle SPI, data written to D is transferred to the shifter almost immediately
so that SPTEF is set within two bus cycles, allowing a second set of data to be queued into the transmit
buffer. After completion of the transfer of the data in the shift register, the queued data from the transmit
buffer automatically moves to the shifter, and SPTEF is set to indicate that room exists for new data in the
transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data
moves from the buffer to the shifter.
If a transfer does not stop, the last data that was transmitted is sent out again.
4
MODF
0 SPI transmit buffer not empty
1 _{SPI transmit buffer empty}
Master mode fault flag
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some
other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when
MSTR is 1, MODFEN is 1, and SSOE is 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1 and then writing to the SPI control register 1 (C1).
3–0
Reserved
0 No mode fault error
1 Mode fault error detected
This field is reserved.
This read-only field is reserved and always has the value 0.
34.3.5 SPI data register (SPIx_D)
This register is both the input and output register for SPI data. A write to the register
writes to the transmit data buffer, allowing data to be queued and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is
transmitted immediately after the previous transmission has completed.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
566
Freescale Semiconductor, Inc.