MKL04Z32VFK4 Datasheet, PDF (640/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Functional description
In the case of a framing error, provided the received character was not a break character,
the sampling logic that searches for a falling edge is filled with three logic 1 samples so
that a new start bit can be detected almost immediately.
36.3.3.2 Receiver wakeup operation
Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the
characters in a message intended for a different UART receiver. In such a system, all
receivers evaluate the first character(s) of each message, and as soon as they determine
the message is intended for a different receiver, they write logic 1 to the receiver wake up
control bit(UART_C2[RWU]). When RWU bit is set, the status flags associated with the
receiver, with the exception of the idle bit, IDLE, when UART_S2[RWUID] bit is set,
are inhibited from setting, thus eliminating the software overhead for handling the
unimportant message characters. At the end of a message, or at the beginning of the next
message, all receivers automatically force UART_C2[RWU] to 0 so all receivers wake
up in time to look at the first character(s) of the next message.
36.3.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a full character time
of the idle-line level. The UART_C1[M] and UART_C4[M10] control bit selects 8-bit to
10-bit data mode and the UART_BDH[SBNS] bit selects 1-bit or 2-bit stop bit number
that determines how many bit times of idle are needed to constitute a full character time,
10 to 13 bit times because of the start and stop bits.
When UART_C2[RWU] is one and UART_S2[RWUID] is zero, the idle condition that
wakes up the receiver does not set the UART_S1[IDLE] flag. The receiver wakes up and
waits for the first data character of the next message that sets the UART_S1[RDRF] flag
and generates an interrupt if enabled. When UART_S2[RWUID] is one, any idle
condition sets the UART_S1[IDLE] flag and generates an interrupt if enabled, regardless
of whether UART_C2[RWU] is zero or one.
The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle
line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the
stop bit and any logic 1s at the end of a character count toward the full character time of
idle. When UART_C1[ILT] is set, the idle bit counter does not start until after the stop bit
time, so the idle detection is not affected by the data in the last character of the previous
message.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
640
Freescale Semiconductor, Inc.