MKL04Z32VFK4 Datasheet, PDF (177/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Field
11
Reserved
10
UART0
9–8
Reserved
7
Reserved
6
I2C0
5–4
Reserved
3–0
Reserved
Chapter 12 System integration module (SIM)
SIM_SCGC4 field descriptions (continued)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
UART0 Clock Gate Control
This bit controls the clock gate to the UART0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
I2C0 Clock Gate Control
This bit controls the clock gate to the I ² C0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 1.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
1
0
0
0
0
W
Reset 0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
SIM_SCGC5 field descriptions
Field
31–20
Reserved
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Freescale Semiconductor, Inc.
177