MKL04Z32VFK4 Datasheet, PDF (598/658 Pages) Freescale Semiconductor, Inc – KL04 Sub-Family Reference Manual

Memory map and register descriptions
I2Cx_FLT field descriptions (continued)
Field
Description
Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by
writing 1 to it.
5
STOPIE
0 No stop happens on I2C bus
1 Stop detected on I2C bus
I2C Bus Stop Interrupt Enable
This bit enables the interrupt for I2C bus stop detection.
NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF
bit by writing 1 to it, and then clear the IICIF bit in the status register. If this sequence is reversed,
the IICIF bit is asserted again.
0 Stop detection interrupt is disabled
1 Stop detection interrupt is enabled
4–0
I2C Programmable Filter Factor
FLT
Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. For any glitch
whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
00h
No filter/bypass
01-1Fh Filter glitches up to width of n bus clock cycles, where n=1-31d
35.3.8 I2C Range Address register (I2Cx_RA)
Address: 4006_6000h base + 7h offset = 4006_6007h
Bit
7
6
5
4
3
2
1
0
Read
RAD
0
Write
Reset
0
0
0
0
0
0
0
0
I2Cx_RA field descriptions
Field
7–1
RAD
0
Reserved
Range Slave Address
Description
This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address
scheme. Any nonzero write enables this register. This register's use is similar to that of the A1 register, but
in addition this register can be considered a maximum boundary in range matching mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
598
Freescale Semiconductor, Inc.