MSC8112 Datasheet, PDF (38/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Hardware Design Considerations
1.1 V
Power supply
or
Voltage Regulator
(I_min = 3 A)
+
-
Maximum IR drop
of 15 mV at 1 A
L_max = 2 cm
Bulk/Tantalum capacitors
with low ESR and ESL
Note: Use at least three capacitors.
Each capacitor must be at least 150 μF.
One 0.01 µF capacitor
for every 3 core supply
pads.
MSC8113
High frequency capacitors
(very low ESR and ESL)
Figure 33. Core Power Supply Decoupling
Each V_CC and V_DD pin on the MSC8112 device should have a low-impedance path to the board power supply. Similarly, each
GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The V_CC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V_CC, V_DD, and GND should
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V_CC and
GND planes.
All output pins on the MSC8112 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V_CC, V_DD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
V_CCSYN-GND_SYN. To ensure internal clock stability, filter the power to the V_CCSYN input with a circuit similar to the one in
Figure 34. For optimal noise filtering, place the circuit as close as possible to V_CCSYN. The 0.01-µF capacitor should be closest
to V_CCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to V_DD. These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GND_SYN. Bypass GND_SYN to V_CCSYN
by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8112 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
V_DD
10Ω
10nH
10 µF
V_CCSYN
0.01 µF
Figure 34. V_CCSYN Bypass
3.3 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
V_DDH or GND, except for the following:
• If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be
disconnected.
• When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either
up or down, depending on design requirements.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
38
Freescale Semiconductor