MSC8112 Datasheet, PDF (17/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

3.3 V
V_DDH = Nominal
V_DD = Nominal
1
Electrical Characteristics
V_DDH Nominal
1.1 V
V_DD Nominal
o.5 V
PORESET/TRST asserted
V_DD applied
CLKIN starts toggling
V_DDH applied
Time
PORESET/TRST deasserted
Figure 7. Start-Up Sequence: V_DD Raised Before V_DDH with CLKIN Started with V_DDH
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
V
3.3 V
B
A
V_DDH (IO)
1.2 V
V_DD/V_CCSYN
Figure 8. Power-Up Sequence for V_DDH and V_DD/V_CCSYN
t (time)
The following rules apply:
1. During time interval A, V_DDH should always be equal to or less than the V_DD/V_CCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2. The duration of timing interval B should be kept as small as possible and less than 10 ms.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
17