MSC8112 Datasheet, PDF (28/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
Figure 15 shows DSI asynchronous write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW¹
100
HRDS²
HDBSn¹
HWBSn²
HD[0–63]
106
HTA³
108
HTA⁴
112
201
101
102
202
109
110
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 15. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram
Figure 16 shows DSI asynchronous broadcast write signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW¹
HRDS²
100
HDBSn¹
HWBSn²
112
201
HD[0–63]
101
102
202
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
Figure 16. Asynchronous Broadcast Write Timing Diagram
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
28
Freescale Semiconductor