MSC8112 Datasheet, PDF (20/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
2.5.4.2 Reset Configuration
The MSC8112 has two mechanisms for writing the reset configuration:
• Through the direct slave interface (DSI)
• Through the system bus. When the reset configuration is written through the system bus, the MSC8112 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
• RSTCONF
• CNFGS
• DSISYNC
• DSI64
• CHIP_ID[0–3]
• BM[0–2]
• SWTE
• MODCK[1–2]
2.5.4.3 Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
1
2
3
5
6
7
8
Note:
Characteristics
Required external PORESET duration minimum
• CLKIN = 20 MHz
• CLKIN = 100 MHz (300 MHz core)
Delay from deassertion of external PORESET to deassertion of internal
PORESET
• CLKIN = 20 MHz to 100 MHz
Delay from de-assertion of internal PORESET to SPLL lock
• CLKIN = 20 MHz (RDF = 1)
• CLKIN = 100 MHz (RDF = 1) (300 MHz core)
Delay from SPLL to HRESET deassertion
• REFCLK = 40 MHz to 133 MHz
Delay from SPLL lock to SRESET deassertion
• REFCLK = 40 MHz to 133 MHz
Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
Hold time from deassertion of PORESET to deassertion of RSTCONF,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
Timings are not tested, but are guaranteed by design.
Expression
16/CLKIN
1024/CLKIN
6400/(CLKIN/RDF)
(PLL reference
clock-division factor)
512/REFCLK
515/REFCLK
Min Max Unit
800
—
ns
160
—
ns
6.17
51.2
µs
320
320
µs
64
64
µs
3.08
12.8
µs
3.10 12.88
µs
3
—
ns
5
—
ns
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
20
Freescale Semiconductor