MSC8112 Datasheet, PDF (35/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

2.5.12 EE Signals
Table 29. EE Pin Timing
Number
Characteristics
Type
Min
65
66
Notes: 1.
2.
EE0 (input)
Asynchronous
4 core clock periods
EE1 (output)
Synchronous to Core clock
1 core clock period
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 28 shows the signal behavior of the EE pins.
65
EE0 in
EE1 out
2.5.13 JTAG Signals
66
Figure 28. EE Pin Timing
Table 30. JTAG Timing
No.
Characteristics
700
701
702
703
704
705
706
707
708
709
710
711
712
713
Note:
TCK frequency of operation (1/(T_C × 4); maximum 25 MHz)
TCK cycle time
TCK clock pulse width measured at V_M = 1.6 V
• High
• Low
TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
All
frequencies
Min Max
0.0
25
40.0
—
20.0
—
16.0
—
0.0
3.0
5.0
—
20.0
—
0.0
30.0
0.0
30.0
5.0
—
20.0
—
0.0
20.0
0.0
20.0
100.0
—
30.0
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
35