MSC8112 Datasheet, PDF (22/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
No.
Characteristic
Ref = CLKIN at 1.1 V
and 100 MHz
10 Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
11a ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
3.1
11b DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising
3.6
edge
11c AACK set-up time before the 50% level of the REFCLK rising edge
3.0
11d TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode
3.5
4.4
12 Data bus set-up time before REFCLK rising edge in Normal mode
• Data-pipeline mode
1.9
• Non-pipeline mode
4.2
13¹ Data bus set-up time before the 50% level of the REFCLK rising edge in ECC
and PARITY modes
• Data-pipeline mode
2.0
• Non-pipeline mode
8.2
14¹ DP set-up time before the 50% level of the REFCLK rising edge
• Data-pipeline mode
2.0
• Non-pipeline mode
7.9
15a TS and Address bus set-up time before the 50% level of the REFCLK rising edge
• Extra cycle mode (SIUBCR[EXDD] = 0)
• No extra cycle mode (SIUBCR[EXDD] = 1)
4.2
5.5
15b Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the
REFCLK rising edge
• Extra cycle mode (SIUBCR[EXDD] = 0)
3.7
• No extra cycle mode (SIUBCR[EXDD] = 1)
4.8
16
17
18
Notes:
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
3.7
IRQx setup time before the 50% level; of the REFCLK rising edge³
4.0
IRQx minimum pulse width³
6.0 + T_REFCLK
1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
3. Guaranteed by design.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
22
Freescale Semiconductor