MSC8112 Datasheet, PDF (19/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
Table 10. Reset Sources
Name
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Software
watchdog reset
Bus monitor reset
Host reset
command through
the TAP
Direction
Input
Input/ Output
Input/ Output
Internal
Internal
Internal
Description
Initiates the power-on reset flow that resets the MSC8112 and configures various attributes of the
MSC8112. On PORESET, the entire MSC8112 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8112. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8112 Reference Manual.
Initiates the soft reset flow. The MSC8112 detects an external assertion of SRESET only if it occurs
while the MSC8112 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system configuration is maintained.
When the MSC8112 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC8112 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
Table 11. Reset Actions for Each Reset Source
Reset Action/Reset Source
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
Power-On
Reset
(PORESET)
External only
Yes
Hard Reset (HRESET)
External or Internal
(Software Watchdog or
Bus Monitor)
No
Soft Reset (SRESET)
External
No
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
No
Yes
No
No
No
Yes
No
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Depends on command
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
V_DD and V_DDH are both at their nominal levels.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
19