MSC8112 Datasheet, PDF (23/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
Table 15. AC Timing for SIU Outputs
No.
30²
31
32a
32b
32c
32d
33a
33b
34
35a
35b
Notes:
Characteristic
Bus Speed in MHz³
Ref = CLKIN at 1.1 V
and 100 MHz
Units
Minimum delay from the 50% level of the REFCLK for all signals
0.9
ns
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
6.0
ns
Address bus max delay from the 50% level of the REFCLK rising edge
• Multi-master mode (SIUBCR[EBM] = 1)
• Single-master mode (SIUBCR[EBM] = 0)
6.4
ns
5.3
ns
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level
6.4
ns
of the REFCLK rising edge
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
6.9
ns
BADDR max delay from the 50% level of the REFCLK rising edge
5.2
ns
Data bus max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode
4.8
ns
7.1
ns
DP max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode
6.0
ns
7.5
ns
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of
5.1
ns
the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising
edge
6.0
ns
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK
rising edge
5.5
ns
1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3
ns from the listed value.
3. The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8112 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8112.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8112 Reference Manual for details.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
23