MSC8112 Datasheet, PDF (27/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Figure 14 shows DSI asynchronous read signals timing.
HCS
HA[11–29]
HCID[0–4]
HDST
HRW¹
HWBSn²
100
Electrical Characteristics
101
HDBSn¹
HRDS²
HD[0–63]
112
103
107
104
106
102
105
109
HTA³
108
110
HTA⁴
111
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with
pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
27