MSC8112 Datasheet, PDF (25/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
2.5.5.2 CLKIN to CLKOUT Skew
Table 17 describes the CLKOUT-to-CLKIN skew timing.
No.
20
21
24
Notes:
Table 16. CLKOUT Skew
Characteristic
Min¹
Max¹
Units
Rise-to-rise skew
0.0
0.95
ns
Fall-to-fall skew
–1.5
1.0
ns
CLKOUT phase (1.1 V, 100 MHz)
• Phase high
• Phase low
3.3
—
ns
3.3
—
ns
1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.
2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3. CLKOUT skews are measured using a load of 10 pF.
4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing
values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
CLKIN
CLKOUT
20
21
Figure 12. CLKOUT and CLKIN Signals.
2.5.5.3 DMA Data Transfers
Table 17 describes the DMA signal timing.
Table 17. DMA Signals
No.
Characteristic
37
DREQ set-up time before the 50% level of the falling edge of REFCLK
38
DREQ hold time after the 50% level of the falling edge of REFCLK
39
DONE set-up time before the 50% level of the rising edge of REFCLK
40
DONE hold time after the 50% level of the rising edge of REFCLK
41
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
Ref = CLKIN
Min
Max
5.0
—
0.5
—
5.0
—
0.5
—
0.5
7.5
Units
ns
ns
ns
ns
ns
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ
according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
25