MSC8112 Datasheet, PDF (37/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Hardware Design Considerations
3 Hardware Design Considerations
The following sections discuss areas to consider when the MSC8112 device is designed into a system.
3.1 Start-up Sequencing Recommendations
Use the following guidelines for start-up and power-down sequences:
• Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
• CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
• If possible, bring up V_DD/V_CCSYN and V_DDH together. If it is not possible, raise V_DD/V_CCSYN first and then bring up
V_DDH. V_DDH should not exceed V_DD/V_CCSYN until V_DD/V_CCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with V_DDH going down first and
then V_DD/V_CCSYN.
Note: This recommended power sequencing for the MSC8112 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply V_DDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if V_DD rises before V_DDH (see Figure 6), current can pass from the V_DD supply through the
device ESD protection circuits to the V_DDH supply. The ESD protection diode can allow this to occur when V_DD exceeds V_DDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
• Never allow V_DD to exceed V_DDH + 0.8V.
• Design the V_DDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial V_DDH level of V_DD – 0.8 V before it is enabled.
After power-up, V_DDH must not exceed V_DD/V_CCSYN by more than 2.6 V.
3.2 Power Supply Design Considerations
When implementing a new design, use the guidelines described in the MSC8112 Design Checklist (AN3374 for optimal system
performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed
design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
• For the core supply, use a voltage regulator rated at 1.1 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
• Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8112 device.
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
37