MSC8112 Datasheet, PDF (29/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

2.5.6.2
DSI Synchronous Mode
Table 19. DSI Inputs in Synchronous Mode
No.
Characteristic
Expression
120
121
122
123
124
125
126
127
Notes:
HCLKIN cycle time^1,2
HCLKIN high pulse width
HCLKIN low pulse width
HA[11–29] inputs set-up time
HD[0–63] inputs set-up time
HCID[0–4] inputs set-up time
All other inputs set-up time
All inputs hold time
1. Values are based on a frequency range of 18–70 MHz.
2. Refer to Table 7 for HCLKIN frequency limits.
HTC
(0.5 ± 0.1) × HTC
(0.5 ± 0.1) × HTC
—
—
—
—
—
Table 20. DSI Outputs in Synchronous Mode
No.
Characteristic
128 HCLKIN high to HD[0–63] output active
129 HCLKIN high to HD[0–63] output valid
130 HD[0–63] output hold time
131 HCLKIN high to HD[0–63] output high impedance
132 HCLKIN high to HTA output active
133 HCLKIN high to HTA output valid
134 HTA output hold time
135 HCLKIN high to HTA high impedance
Electrical Characteristics
1.1 V Core
Min
Max
10.0
55.6
4.0
33.3
4.0
33.3
1.2
—
0.6
—
1.3
—
1.2
—
1.5
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
1.1 V Core
Min
Max
2.0
—
—
7.6
1.7
—
—
8.3
2.2
—
—
7.4
1.7
—
—
7.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
120
HCLKIN
122
121
123
127
HA[11–29] input signals
124
127
HD[0–63] input signals
125
127
HCID[0–4] input signals
126
127
All other input signals
131
129
128
130
HD[0–63] output signals
133
132
HTA output signal
135
134
Figure 17. DSI Synchronous Mode Signals Timing Diagram
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
29