MSC8112 Datasheet, PDF (2/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Table of Contents
1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .14
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .37
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .37
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .37
3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .38
3.4 External SDRAM Selection . . . . . . . . . . . . . . . . . . . . . .40
3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .40
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
List of Figures
Figure 1. MSC8112 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore^® SC140 DSP Extended Core Block Diagram . 3
Figure 3. MSC8112 Package, Top View. . . . . . . . . . . . . . . . . . . . . 5
Figure 4. MSC8112 Package, Bottom View . . . . . . . . . . . . . . . . . . 6
Figure 5. Overshoot/Undershoot Voltage for V_IH and V_IL. . . . . . . 15
Figure 6. Start-Up Sequence: V_DD and V_DDH Raised Together . . 16
Figure 7. Start-Up Sequence: V_DD Raised Before V_DDH with CLKIN
Started with V_DDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Timing Diagram for a Reset Configuration Write . . . . . 21
Figure 10.Internal Tick Spacing for Memory Controller Signals. . . 21
Figure 11.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 25
Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15.Asynchronous Single- and Dual-Strobe Modes Write
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16.Asynchronous Broadcast Write Timing Diagram . . . . . . 28
Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . . 29
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 23.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . . 32
Figure 24.MII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 25.RMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 36
Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . 36
Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 36
Figure 32.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 38
Figure 34.V_CCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 35.MSC8112 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
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Freescale Semiconductor