MSC8112 Datasheet, PDF (34/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

2.5.10.4 SMII Mode
Table 27. SMII Mode Signal Timing
No.
Characteristics
808
809
810
Notes:
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
1. Measured using a 5 pF load.
2. Measured using a 15 pF load.
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD
808
809
Valid
810
Valid
Figure 26. SMII Mode Signal Timing
2.5.11 GPIO Timing
Table 28. GPIO Timing
No.
Characteristics
601 REFCLK edge to GPIO out valid (GPIO out delay time)
602 REFCLK edge to GPIO out not valid (GPIO out hold time)
603 REFCLK edge to high impedance on GPIO out
604 GPIO in valid to REFCLK edge (GPIO in set-up time)
605 REFCLK edge to GPIO in not valid (GPIO in hold time)
REFCLK
603
GPIO
(Output)
GPIO
(Input)
High Impedance
604
605
Valid
Figure 27. GPIO Timing
Min Max Unit
1.0
—
ns
1.0
—
ns
1.5¹
6.0²
ns
Valid
Ref = CLKIN
Min
Max
—
6.1
1.1
—
—
5.4
3.5
—
0.5
—
Unit
ns
ns
ns
ns
ns
601
602
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
34
Freescale Semiconductor