MSC8112 Datasheet, PDF (26/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

Electrical Characteristics
REFCLK
DREQ
38
37
40
39
DONE
41
DACK/DONE/DRACK
Figure 13. DMA Signals
2.5.6 DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table 18. DSI Asynchronous Mode Timing
No.
100
101
102
103
104
105
106
107
108
109
110
111
112
201
202
Notes:
Characteristics
Min
Max
Attributes¹ set-up time before strobe (HWBS[n]) assertion
Attributes¹ hold time after data strobe deassertion
1.5
—
1.3
—
Read/Write data strobe deassertion width:
• DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
• DCR[HTAAD] = 0
Read data strobe deassertion to output data high impedance
—
1.8 + T_REFCLK
5 + T_REFCLK
5 + (1.5 × T_REFCLK)
5 + (2.5 × T_REFCLK)
1.8 + T_REFCLK
—
8.5
Read data strobe assertion to output data active from high impedance
2.0
—
Output data hold time after read data strobe deassertion
2.2
—
Read/Write data strobe assertion to HTA active from high impedance
2.2
—
Output data valid to HTA assertion
Read/Write data strobe assertion to HTA valid²
3.2
—
—
7.4
Read/Write data strobe deassertion to output HTA high impedance.
—
6.5
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
Read/Write data strobe deassertion to output HTA deassertion.
—
6.5
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
• DCR[HTADT] = 01
• DCR[HTADT] = 10
• DCR[HTADT] = 11
Read/Write data strobe assertion width
Host data input set-up time before write data strobe deassertion
—
1.8 + T_REFCLK
1.0
5 + T_REFCLK
5 + (1.5 × T_REFCLK)
5 + (2.5 × T_REFCLK)
—
—
Host data input hold time after write data strobe deassertion
1.7
—
1. Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3. All values listed in this table are tested or guaranteed by design.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
26
Freescale Semiconductor