MSC8112 Datasheet, PDF (3/44 Pages) Freescale Semiconductor, Inc – Dual Core Digital Signal Processor

SC140
Extended Core
SC140
Extended Core
MQBus
Boot
ROM
M2
RAM
128
128
64
IP Master
Memory
Controller
SQBus
Local Bus
32 Timers
UART
RS-232
PLL/Clock _PLL
JTAG Port _JTAG
IPBus
32
System
Interface
64 Internal Local Bus
DMA
Bridge
Internal System Bus
SIU
Registers
64
4 TDMs
GPIO
GIC
8 Hardware
Semaphores
Ethernet
GPIO Pins
Interrupts
MII/RMII/SMII
Direct
Slave
Interface
(DSI)
DSI Port
32/64
Memory
System Bus
Controller _32/64
Figure 1. MSC8112 Block Diagram
Program
Sequencer
Address
Register
File
SC140
Core
Address
ALU
JTAG
EOnCE
Power
Management
Data ALU
Register
File
Data
ALU
SC140 Core
64
Xa
64
Xb
128
P
Instruction
Cache
128
QBus
PIC
IRQs
LIC
QBus
Bank 1
M1
RAM
QBC
QBus
Bank 3
QBus
Interface
IRQs
MQBus
SQBus
128
128
Local Bus
64
Notes: 1. The arrows show the data transfer direction.
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines
four QBus banks. In addition, the QBC handles internal memory contentions.
Figure 2. StarCore^® SC140 DSP Extended Core Block Diagram
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0
Freescale Semiconductor
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