XRS10L620 Datasheet, PDF (43/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

7.2 Command List Structure
XRS10L620 Rev 1.00
Total 32 Command Headers are defined with 4-DW(16 bytes) each that details the direction, type, and scatter/gather pointer
of the command. The Command List is aligned in 1024 bytes.
Further details of each field are listed below.
DW# Bit#
Description
31:16 Reserved
15:12 Port Multiplier Port(PMP): Indicates the port number that should be used when constructing
data FISes on transmit, and to check against all FISes received for this command.
11 Data phase flag.
10 Clear Busy upon R_OK(C): When set, the HBA shall clear PxTFD.STS.BSY and PxCI bit
after transmitting this FIS and receive R_OK, no need to wait the relative D2H FIS.
Host mode : Set to one for first H2D FIS of soft reset sequence
DW0 09 BIST(B): reserved
08 Reserved
07 Prefetchable(P): When set, the HBA will prefetch 8 more PRDs during Data FIS transfer.
The bit is not available if NCQSW or MultiPM bits are enabled(PxAIE bit1,0)
06 Write(W): When set, the direction is device write (data from system memory to device)
05 ATAPI(A): When set, indicates a PIO setup FIS shall be sent by the device indicating a
transfer for the ATAPI packet.
04:00 Command FIS Length(CFL): Length of the Command FIS, in DW.
DW1 31:00 Reserved
31:07 Command Table Base Address(Low):low 32 bits physical address pointer to the command
DW2
table that is 128-byte aligned
06:00 Reserved
31:07 Command Table Base Address(High):high 32 bits physical address pointer.
DW3
06:00 Reserved
7.3 Command Table and PRD table
The table contains the command FIS, ATAPI Command, and PRD table as shown in Fig6.1.
It is aligned in 128 bytes.
The Command FIS field contains the H2D FIS to be sent to the device. The DWord count is same as CFL field in Command
Header.
The ATAPI Packet field contains either 12 or 16 bytes to transmit if ‘A’ bit is set in the Command Header.
42
1/20/2009