XRS10L620 Datasheet, PDF (23/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
31:24 R 00h RXRS As Slave, last byte received via I2C
23:16 R 00h RXRM As Master, the byte content received via I2C
15:08 W
TXR As Master, the byte content to transmit via I2C
07
W
STA Generate START condition
06
W
STO Generate STOP condition
05
W
RD As Master, read from slave
04
W
WR As Master, write to slave
03
W
AC ACK, when as receiver, ‘0’ to sent ACK, ‘1’ sent NACK
02 RW
IFS Enable interrupt flag (Reg_008H bit 31) to INTA# when as slave
01 RW
IFM Enable interrupt flag (Reg_008H bit 30) to INTA# when as master
00
R
TIP ‘1’=Transfer In Progress; ‘0’=transfer complete
Reg_0B4H (IOG+B4h) : Reserved
Test only for 32 bit seed value
Reg_0B8H to Reg_0FFH (IOG+B8h to FFh ) : Reserved
6.3.2 Port Registers (length 80h bytes per port/channel):
SATA Port 0 address = Reg_100H to Reg_17FH =(IO01+00h to 7Fh)
SATA Port 1 address = Reg_180H to Reg_1FFH =(IO01+80h to FFh)
Reg address
from offset
Symbol
Description
00 – 03
PxCLB
Port x command list base address
04 – 07
PxCLBU
Port x command list base address upper 32bits
08 – 0B
PxFB
Port x FIS base address
0C – 0F
PxFBU
Port x FIS base address upper 32bits
10 – 13
PxIS
Port x interrupt status
14 – 17
PxIE
Port x interrupt enable
18 – 1B
PxCMD
Port x command
1C – 1F
PxPRBS40B_PAT User defined pattern for internal test
20 – 23
PxTFD
Port x task file data
24 – 27
PxSIG
Port x signature
28 – 2B
PxSSTS
Port x SCR0: SStatus
2C – 2F
PxSCTL
Port x SCR1: Scontrol
30 – 33
PxSERR
Port x SCR2: Serror
34 – 37
PxSACT
Port x SCR3: Sactive
22
1/20/2009