XRS10L620 Datasheet, PDF (12/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
6. Register Definition
6.1 PCI Configuration Memory Registers :
( RWC : write 1 to clear )
( RW1 : write 1 to enable the bit and will be auto-cleared; write 0 has no function )
Addr
00,01
02,03
04,05
06,07
08
09
0A
0B
0C
0D
0E
0F
10-13
R/W
Name
Description
R
Vendor ID
1191h
R
Device ID
000Dh, 000Eh, 000Fh, depend on RA1,0 setting
RW Command Register ^{Bit0 = 1 : enable IO space}
= 0: disable IO space
Bit1 = 1 : enable Memory space
= 0: disable Memory space
Bit2 = 1 : enable Bus Master
= 0: disable Bus Master
Bit6 = 1 : enable Parity error response
= 0: disable Parity error response
Bit10 = 1 : disable INTA#
= 0: enable INTA#
Other bits are ‘0’, read only
R
Status Register ^{Bit3 = reflect the interrupt status}
Bit4 = 1 : with PCI power management capability
Bit5 = 1 : 66 MHz capable
Bit7 = 0 : Fast Back to Back Capable
Bit8 = 1 : Data parity error detected by master
Bit10,9 = 0,1 : medium DEVSEL timing
Bit13 = 1 : Received Master abort
Bit15 = 1 : Detected parity error by device
R
Revision ID
00h
R Programming Interface ^00h
R
SubClass
00H (SCSI) or 04H(RAID),
by DCS0#/RA11 configuration
R
Basic Class
01h, mass storage
RW
Cache Line Size ^00h
RW
Latency Timer ^{(00h, default)}
The register specify PCI clock count for this PCI master
R
Header type
00h
R
BIST
00h
RW
Base Addr Reg0 ^{IO address of Global host & IDE registers, length 256}
bytes
11
1/20/2009