XRS10L620 Datasheet, PDF (28/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

15
R
0
14
R
0
13
R
0
12:08 R
0
07:06 R
0
05 RW 0
04 RW 0
03 RW1 0
02
R
1
01 RW RA2
00 RW 0
XRS10L620 Rev 1.00
Command list running,
CR
Indicates command list DMA engine of this port is running
FIS receive running,
FR
Indicates FIS receive DMA engine of this port is running
ISS Reserved
CCS Current working command slot number in one of P0CI
Reserved
0 = normal reset level of ST (bit0)
1 = deeper reset level of ST, issue COMRESET on the channel
FIS receive enable,
FRE ‘1’ will post received FIS to host memory pointed by PxFB.
Software must not set the bit until PxFB is a valid pointer.
Command list override, set the bit will clear PxTFD.STS.BSY and
PxTFD.STS.DRQ so that software reset could be issued regardless
BSY and DRQ bit value.
CLO
The bit is auto-cleared to 0 when BSY & DRQ are cleared.
Writing the bit with 0 has no effect.
Host mode only.
POD Power on device, reserved to 1
Spin-up device. Set and clear this bit by software.
SUD Writing the bit from 0 to 1 to issue COMRESET to the device
Kept as‘1’for normal operation
Start switch of command list DMA engine.
ST ^{Writing the bit from 0 to 1 starts processing from PxCI bit 0.}
Writing the bit from 1 to 0 will clear PxCI register.
Different reset level is switched with bit5.
Reg_11CH (IO01+1Ch) : P0PRBS40B_PAT
User-defined pattern in PRBS check for internal test only.
Reg_120H (IO01+20h): P0TFD, Task file data of this port
The register copies specific fields of the task file when FISes are receive, like
z D2Hregister FIS
z PIO Setup FIS
z Set Device Bits FIS(not include BSY and DRQ bits)
For MultiPM bit (Reg_174H bit 1)= 0 :
The field is the received D2H Register FIS from all PM#0 to #15 devices, may be overlapped.
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1/20/2009