XRS10L620 Datasheet, PDF (38/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

1 RW 0
0 RW 0
SQLCHENB
PDRX
XRS10L620 Rev 1.00
Squelch circuit enable signal
0 = Enable squelch circuit 1 = Disable squelch circuit
1 = Power down RX lane
0 = Not power down RX lane
Reg_160H to Reg_16FH (IO01+60h to 6Fh) :
Port 0 Task File registers for Port Multiplier #1 to #7
These fields are valid only when Reg_174H bit 1 ( P0MultiPM) is‘1’ for FIS-based switching
Reg_160H (IO01+60h) : PxTFD1 for PM# 1
Bit(s) R/W default Symbol
Description
31:24 R
0h
ERR1 ^{PortX, PM#1 Task file error register}
23:16 R
7Fh
STS1 ^{PortX, PM#1 Task file status register, with BSY, DRQ, ERR bits}
15:08 R
0h
ERRF ^{PortX, PM#F Task file error register}
07:00 R
0h
STSF ^{PortX, PM#F Task file status register, with BSY, DRQ, ERR bits}
Reg_164H (IO01+64h) : PxTFD23 for PM# 2,3
Bit(s) R/W default Symbol
Description
31:24 R
0h
ERR3 ^{PortX, PM#3 Task file error register}
23:16 R
7Fh
STS3 ^{PortX, PM#3 Task file status register, with BSY, DRQ, ERR bits}
15:08 R
0h
ERR2 ^{PortX, PM#2 Task file error register}
07:00 R
7Fh
STS2 ^{PortX, PM#2 Task file status register, with BSY, DRQ, ERR bits}
Reg_168H (IO01+68h): PxTFD45 for PM# 4,5
Bit(s)
31:24
23:16
R/W default
R
0h
R 7Fh
Symbol
Description
ERR5 ^{PortX, PM#5 Task file error register}
PortX, PM#5 Task file status register, with BSY, DRQ, ERR bits
STS5
15:08 R
0h
ERR4 ^{PortX, PM#4 Task file error register}
PortX, PM#4 Task file status register, with BSY, DRQ, ERR bits
07:00 R 7Fh STS4
Reg_16CH (IO01+6Ch): PxTFD67 for PM# 6,7
Bit(s) R/W default Symbol
Description
31:24 R
0h
ERR7 ^{PortX, PM#7 Task file error register}
PortX, PM#7 Task file status register, with BSY, DRQ, ERR bits
23:16 R 7Fh STS7
15:08 R
0h
ERR6 ^{PortX, PM#6 Task file error register}
PortX, PM#6 Task file status register, with BSY, DRQ, ERR bits
07:00 R 7Fh STS6
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1/20/2009