XRS10L620 Datasheet, PDF (29/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

For MultiPM bit (Reg_174H bit 1)= 1 :
XRS10L620 Rev 1.00
The field is the received D2H Register FIS from only PM#0 device, no overlap with other PM#.
Bit(s) R/W default Symbol
Description
31:16 R
0h
Reserved
15:08 R
0h
ERR Task file error register
07:00 R 7Fh
Task file status register, with 3 bits that may affect AHCI
STS
Bit7 : BSY
Bit3 : DRQ
Bit0 : ERR
Reg_124H (IO01+24h) : P0SIG, signature of this port
For MultiPM bit (Reg_174H bit 1)= 0 :
The field is the received D2H Register FIS from all PM# devices, may be overlapped.
For MultiPM bit (Reg_174H bit 1)= 1 :
The field is the received D2H Register FIS from only PM#0 device, no overlap with other PM#.
Bit(s)
31:00
R/W default
FFFF-
R
FFFFh
Symbol
Description
Bit 31:24 : Cylinder high register (LBA [23:16])
Bit 23:16 : Cylinder low register (LBA [15:08])
SIG _{Bit 15:08 : Sector number register (LBA [07:00])}
Bit 07:00 : Sector count register
Reg_128H (IO01+28h) : P0SSTS (SCR0 : SStatus)
Bit(s) R/W default Symbol
Description
31:12 R
0
Reserved
11:08 R
0h
07:04 R
0h
03:00 R
0h
Indicates the current power state :
0h : Device not present or communication not established
IPM
1h : Active state
2h : Partial power management state
6h : Slumber power management state
All other values reserved
Indicates the negotiated speed :
0h : Device not present or communication not established
SPD 1h : Gen 1 rate negotiated
2h : Gen 2 rate negotiated
All other values reserved
Device detection and Phy state
0h : No device detected and Phy not ready
1h : Device presence detected but Phy not ready
DET 3h : Device presence detected and Phy ready
4h : Phy in offline since bus disabled or bus in a BIST loopback
mode
All other values reserved
Reg_12CH (IO01+2Ch) : P0SCTL (SCR2 : SControl)
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1/20/2009