XRS10L620 Datasheet, PDF (32/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

31:00 RW1 0h
CICLR
XRS10L620 Rev 1.00
Force CI and SACT bits cleared by host
Fill‘1’ to clear the respective CI/SACT bit, then the‘1’ will
self-cleared to ‘0’.
Only these CI bits belong to the same PM number can be cleared
at a time. The PM# must be assigned at Reg_13FH bit[3:0] before
this register is written
Reg_144H (IO01+44h) : P0SDBFG
Bit(s) R/W Default Symbol
Description
31:00 RWC 0h
SDBFG
Set by the 32 Act bits of Set Device Bits FIS
Cleared by software when writing ‘1’ to each bit
Reg_148H to Reg_15FH (IO01+48h to 5Fh) : Registers for internal test.
Addr
Name
Byte 3
Byte 2
Byte 1
Byte 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
48h Debug 0
0
0
0
4Ch Debug 1 ⁰
0
0
0
0
0
0
50h PHYCTRL
54h PLLTEST
31
1/20/2009